CHECK OUT SPRING 2010 COURSE WEB

Announcements:

Please submit a paragraph description of your project by next Monday March 23. Also, submit a 1-page progress report on your project by April 9.

Description:

Functional Verification consumes a big portion of the overall design cycle. This task is complicated with the increasing size and complexity of designs. In this class, we will read and discuss research papers on verification of concurrent systems. Students will gain an understanding of some core and state of the art solutions in verification of concurrent systems. These systems include hardware as well as software systems. SoCs, parallel programs.

Each student is expected to do an exhaustive research on the chosen topics. The presentations need to be discussed with the instructor before class presentation. The term projects will be written in a research paper format.

Grading will be done based on class presentations, class participation, term project and term paper.

Topics of interest are as follows:

  • - Dynamic verification techniques: simulation-based verification, predictive verification, Dynamic Partial Order Reduction (DPOR), test benches, slicing.
  • - Debugging, Error Diagnosis
  • - Coverage techniques: simple, functional, mutation based coverage
  • - System level verification techniques: SystemC, virtual prototyping/verification.
  • - Formal verification techniques: model checking, temporal logic, Binary Decision Diagrams (BDD), SAT, assertion based verification, System Verilog Assertion (SVA), Partial Order Reduction, Bounded Model Checking (BMC).
  • - Equivalence checking: combinational and sequential equivalence checking
  • - Automated deadlock and race detection
  • - Emulation, FPGA prototyping based verification
  • - Design validation techniques

    • See the syllabus for the list of papers.

    Contact:

    Email: alper DOT sen AT boun DOT edu DOT tr