RH(+): THE MODEL FOR HIGH-LEVEL EMBEDDED SYSTEM DESIGN ON RUN-TIME RECONFIGURABLE HARDWARE

2007

The process of embedded system design on reconfigurable architectures needs smart solutions to reduce the cost of development life-cycle and to use resources efficiently at run time. However, the current solutions (SystemC/xtUML), which are extended from the traditional languages (C++/UML), are insufficient for that. Inefficiency occurs due to: detailed operator definition requirement, forcing user to pay attention low-level design problems at higher levels, complex hardware abstraction procedures,misguiding user during mapping software to hardware, not permitting user to define constraints at the level having software intermediate representation, and outputs lacking of performance from high levels to lower levels. Therefore, the traditional methods must only be used for what they are designed, in order to benefit from them efficiently.

In this thesis, we propose: (1) RH(+); a brand new high level embedded system design model for run-time reconfigurable architectures, solving the aforementioned inefficiency problems, (2) LRH(+); a brand new design language which is not extended from any traditional languages, (3) FRH(+); the framework meeting RH(+) requirements. In our work, we have the tools for developing board support package, defining miscellaneous operators, generating graphs for user interactions, profiling, resource scheduling, finding possible paths with their execution delays, and run-time emulation of reconfigurable hardware.