Configurable Design And FPGA Implementation of The Rijndael Algorithm–The Advanced Encryption Standard

2003

Rijndael is a cryptographic algorithm, which is accepted as an international standard to achieve secure data transfer between digital communication systems. After various attacks to crack the previous encryption standard, DES, a new encryption standard is needed to be developed to achieve data privacy and authenticity in digital communication systems. After a worldwide competition, Rijndael has been selected by US National Institute of Standards and Technology (NIST) and announced as Advanced Encryption Standard (AES). The Rijndael algorithm mainly consists of a symmetric block cipher that can process data blocks of 128, 192 or 256 bits, using key lengths of 128, 196 and 256 bits. After the selection of AES, hardware implementation of the algorithm became highly attractive to provide the cryptographic algorithm agility, physical security and potentially much higher performance than software solutions. The work done in this thesis is the design and implementation of a configurable and fully flexible encryptor, decryptor and combined encryptor-decryptor modules that can be synthesized for any set of data and key size of 128, 192 or 256. All the designs in this work are fully coded in VHDL. In order to give a variety to the work, three different configurable cores have been designed. Also the modules are tried to be designed as configurable and as flexible as possible to be re-used in any kind of design. The modules are designed by using Electronic Code Book (ECB) mode that is basic element of all other block cipher operation modes. After the design, AES block cipher has been simulated and synthesized for different sets of data and key size and the results have been compared.